1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, dynamic random access memories (hereinafter referred to as DRAM) capable of performing a refresh operation in a page mode.
2. Description of the Background Art
FIG. 13 is a block diagram showing one example of a DRAM structure.
The structure and operation of the DRAM will be described with reference to the drawing.
A memory cell array includes memory cells (Mil to Mkq) arranged in a matrix of rows and columns. Each memory cell comprises one n type transistor and one capacitor. A plurality of pairs of bit lines are provided to correspond to memory cells in a column direction. A plurality of word lines are provided to correspond to memory cells in a row direction. Each memory cell is provided at a cross-over point of a word line and one of the bit lines of a bit line pair. Sense amplifiers Sal to Saq receiving a signal .phi.sa are provided to the respective bit line pairs. Each bit line pair is connected to input/output lines IO and IO connected to a write circuit 3 and an output circuit 5. An n type transistor is connected to the bit lines of each pair of bit lines in between each sense amplifier and the input/output lines, a gate of which transistor is connected to a column decoder 12. A precharge potential Vb is applied to the other end of each of bit line pair through a transistor having a gate receiving a signal .phi.E. Word lines WLi-WLk are connected to a row decoder 11. Row decoder 11 is connected to a row address buffer circuit 7 for holding an applied row address and a word line driving circuit 8 for driving a predetermined word line.
Operation of the DRAM will be briefly described in the following.
Selection of a memory cell is done for each cross-over point of one word line and one bit line selected by row decoder 11 and column decoder 12 based on row and column address data input to a terminal 1. An ordinary write to such a selected memory cell as described above is done by applying data (Din) input from a terminal 2 across bit lines of a predetermined bit line pair as a potential difference through input/output lines IO and IO. The potential of the bit line connected to the selected memory cell is held by the capacitor. In a read operation, the potential held by the selected memory cell, the potential developing as the potential difference between the bit lines of the bit line pair connected to the memory cell, is amplified and the amplified potential is output as data (Dout) through input/output lines IO and IO by the selection of the output gate by column decoder 12.
The foregoing description is made on a common read and write operations. A read operation of a DRAM in a page mode will be described. The page mode reading is a reading operation carried out by externally and sequentially outputting a potential difference developed across bit lines of each bit line pair by a selected word line.
FIG. 14 is a waveform diagram of respective signals explaining the page mode reading operation.
For the purpose of simplicity, description will be given by assuming that "1" is written in all the memory cells as electric charge information.
Bit line equalize signal .phi..sub.E is brought down to a low level from a high level in response to the change of an RAS signal from a high level to a low level (at time t.sub.1). In response to the change, row address buffer circuit 7 accepts a row address Xi input to terminal 1 to bring a word line WLi corresponding to the row address from a low level to a high level. The potential rise of word line WLi results in the read of the information charges held by memory cells Mil to Miq connected to the word line onto bit lines Bl to Bq. With the bit lines constituting bit line pairs having been precharged to a potential of 1/2.multidot.Vcc by bit line equalize signal .phi..sub.E, the potentials read from the memory cells develop predetermined potential difference between the bit lines constituting the bit line pairs. Activating the potential differences between the bit lines by sense amplifiers Sal to Saq results in amplification of respective potential differences between bit lines Bl and Bl to between Bq and Bq.
Assuming that an address Ym is input to address input terminal 1 after the activation of the sense amplifiers, the address is accepted as a column address by column address buffer circuit 9. As a result, an input/output line IO gate control signal Ym output from column decoder 12 changes from a low level to a high level (at time t2). Consequently, information data of memory cell Mim, that is, the potential difference developed between the bit lines of Bm and Bm is transmitted to output circuit 5 through input/output lines IO and IO.
Another column address (suppose Yn) input to address terminal 1 is internally accepted by bringing CAS from a low level to a high level (time t4). Output circuit 5 is disconnected from an output terminal 4 simultaneously with the acceptance of the column address, causing output terminal 4 to enter a high impedance state (HiZ). In this state, the internally accepted column address Yn controls column decoder 12 to bring IO gate control signal Yn from a low level to a high level. Subsequently, data of memory cell Min is transmitted to output circuit 5 through bit lines Bn and Bn and input/output lines IO and IO in this way. The data thus transmitted to output circuit 5 is externally output through output terminal 4 in the same manner as described above. Repetition of such operation sequentially reads data (Mil-Miq) of one row.
When reading of the data held in memory cells in one row or only required memory cells in one row is finished, RAS signal and CAS signal are brought from a low level to a high level (time t6). Then, word line WLi and sense amplifier drive signal .phi.sa are brought down from a high level to a low level. Then bit line equalize signal .phi..sub.E is brought from a low level to a high level to maintain the potential on all the bit lines at a precharge potential in order to be ready for reading of a subsequent row. A page mode reading operation for one row address signal is completed in this way.
A page mode writing operation will be described in the following. For the purpose of simplicity, description is made of a case where information "H" is written to all the memory cells with information "L" already written therein.
FIG. 15 is a waveform diagram of the respective signals illustrating the page mode writing operation.
RAS signal is changed from a high level to a low level (time t1), which is followed by a change of bit line equalize signal .phi..sub.E from a high level to a low level. In this state, row address buffer circuit 7 accepts a row address Xi input to address terminal 1 to operate word line driving circuit 8, thereby changing word line WLi corresponding to the input row address Xi from a low level to a high level. The potential rise of word line WLi results in reading of the data held by memory cells Mil-Miq onto respective bit lines Bl-Bq. Sense amplifier activation signal .phi.sa is then changed from a low level to a high level to activate sense amplifiers Sal-Saq, thereby amplifying potential differences appearing between the bit lines.
Then an address, assumed to be Ym, input to address terminal 1 is accepted by column address buffer circuit 9 as a row address. Column decoder 12 changes IO gate control signal Ym from a low level to a high level based on the column address data (time t2). As a result, the data held by memory cell Mim is transmitted to output circuit 5 through bit lines Bm and Bm and input/output lines IO and IO.
Data (Din) applied to data input terminal 2 is applied to input/output lines IO and IO through write circuit 3 by changing CAS signal from a high level to a low level (time t3). At the same time, IO gate control signal Ym corresponding to the column address Ym input to address terminal 1 again changes from a low level to a high level. The acceptance of the column address is made by accepting an input address as a column address at the time of the change of CAS signal from a high level to a low level. Thus, the data applied to data input terminal 2 is written in memory cell Mim through write circuit 3 and input/output lines IO and IO. In this writing, signal W is maintained at a low level prior to the change of signal CAS from a high level to a low level.
Then, signal CAS is changed from a low level to a high level (time t4) after the completion of write of the externally applied data to memory cell Mim.
Repetition of such operation results in writing of external data to a memory cell (Mil-Miq) corresponding to an arbitrary column address.
At the completion of writing of data of one row or only the necessary data in one row, signals RAS, CAS and W are changed from a low level to a high level (time t6). Then, word line WLi and sense amplifier driving signal .phi.sa are changed from a high level to a low level. Furthermore, bit line equalize signal .phi..sub.E is changed from a low level to a high level to prepare for reading and writing of the subsequent row. Write of row address Xi in a page mode is completed in this way. The same operation enables the same page mode writing for another row address.
Brief description will be given to a refresh operation which should be performed in a cycle other than a reading operation or a writing operation.
Like a reading operation, RAS signal is first changed from a high level to a low level, whereby row address buffer circuit 7 accepts a row address input to address terminal 1. Word line WLi corresponding to the accepted row address is changed from a low level to a high level by activating word line driving circuit 8. Such potential rise of word line WLi results in the reading of the data held by memory cells Mil-Miq onto bit lines Bl-Bq, respectively. Then sense amplifier activation signal .phi.sa is changed from a low level to a high level to activate sense amplifiers Sal-Saq, thereby amplifying potential differences appearing between bit line pairs of Bl and Bl to Bq and Bq. High level or low level data corresponding to the previously written data are re-written in memory cells Mil-Miq connected to word line WLi based on such amplified potential differences. RAS is changed from a low level to a high level at the completion of the re-write of data. Then, word line WLi and sense amplifier driving signal .phi.sa are changed from a high level to a low level. Bit line equalize signal .phi..sub.E is changed from a low level to a high level to prepare for a refresh operation of another row. Memory cell data in one row of row address Xi is refreshed in this way.
Repetition of the operation for each row in the manner as described above results in refreshing of the whole memory cells. In a case of a DRAM comprising a memory cell array of p rows .times. q columns, for example, p time repetition of the refresh operations completes the refreshing of the entire memory cell array.
As described above, a memory cell of a DRAM comprising one transistor and one capacitor has electric charges stored therein being constantly lost as a small amount of leakage current. It is therefore necessary to perform such a refresh operation as described above at predetermined intervals to constantly maintain the amount of electric charges stored in the memory cell at a level above a fixed value. A refresh operation results in electric charges held in a memory cell being once read onto a bit line connected to the memory cell. A refresh operation therefore can not be done in a case where a potential appearing between bit lines is successively output or written in a page mode operation and the like. For a conventional DRAM, a refresh operation should be performed by interrupting a reading or a writing operation at predetermined intervals.